1. Field of the Invention
This invention relates to the general field of computers and digital design, and more particularly, to an apparatus and method for synchronizing signals traveling between clock domains in a digital system.
2. Art Background
A digital system frequently employs a plurality of digital subsystems. When these digital subsystems operate in conjunction with the same clock in synchronous fashion, synchronization of signals traveling between these digital subsystems is not necessary. If, however, these digital subsystems operate in conjunction with different clocks, signals traveling between these digital subsystems must be synchronized. For example, a computer system may operate at one frequency but the processor may operate at another frequency.
The asynchronous interface circuit that permits the transferring of data from one clock domain to another is known as a synchronizer. Without such synchronization, metastability problems produce invalid logic results, and this causes the digital system to fail. Metastability arises when the signal input to a flip flop in a particular clock domain does not meet the set-up or hold time requirements of that flip flop. In essence, in order for a flip flop in a first clock domain to function properly, its input signal must be stable for a certain period of time before the flip flop is clocked (set-up time), and remain stable for a certain period of time after the flip flop is clocked (hold time). A signal from a second clock domain, which is not synchronized with the clock of the first clock domain, may not necessarily meet these requirements. As a result, such an input signal can place the flip flop in a "metastable state" wherein its output is momentarily somewhere between logic 0 and logic 1. The flip flop will eventually settle to a proper logic level after a finite period of time termed "the resolution time." During the time the flip flop is in the metastable state, the flip flop produces unpredictable logic results that can cause system failure. Accordingly, a synchronizer circuit must confront and resolve the problem of metastability.
Referring now to FIG. 1, a digital system 100 having two clock domains and a prior art synchronizer is illustrated in block diagram form. System 100 can be viewed as being comprised of three major blocks. The first two blocks, clock domain X 110 and clock domain Y 120, contain all the logic elements for each of the two clock domains, respectively. The third block, synchronizer block 130, contains all the logic elements that are used to synchronize signals passing between the two clock domains. The system also includes an X clock for providing clocking to clock domain X, and a Y clock for providing clocking to clock domain Y.
The synchronizer block is formed by two sub synchronizer blocks: XY synchronizer 140 and YX synchronizer 150. Signal S(XY) to be transmitted from clock domain X 110 to clock domain Y 120 is coupled from clock domain X 110 to XY synchronizer block 140. Block 140 synchronizes signal S(XY) from clock domain X 110 and provides synchronized signal S'(XY) to clock domain Y 140. Similarly, signal S(YX) to be transmitted from clock domain Y 120 to clock domain X 110 is coupled from clock domain Y 120 to YX synchronizer block 150. Block 150 synchronizes signal S(YX) from clock domain Y 120 and provides synchronized signal S'(YX) to clock domain X 110. As illustrated in FIG. 1, both the X clock and the Y clock provide clocking to synchronizer block 130 which utilizes this clocking to accomplish the synchronization of signals.
XY synchronizer 140 and YX synchronizer 150 are comprised of similar parts and operate similarly. Both synchronizers 140 and 150 are formed by an input flip flop, a settling flip flop and an output flip flop. The input flip flop is clocked by the clock of the domain from which the signal is being received. The settling and output flip flops are clocked by the clock of the domain to which the signal is being transmitted. Thus, for XY synchronizer 140, flip flop 142 is the input flip flop. Input flip flop 142 is clocked by the X clock and receives signal S(XY) as its input. Flip flops 144 and 146 are, respectively, the settling and output flip flops for XY synchronizer 140. Flip flops 144 and 146 are both clocked by the Y clock. Settling flip flop 144 receives the output from input flip flop 142 (clocked at the X clock) and allows the signal to settle for one Y clock period before passing the signal to output flip flop 146. Output flip flop 146 then holds the signal provided by settling flip flop 144 for one Y clock period before providing the synchronized output signal S(XY) to clock domain Y 120.
Without settling flip flop 144, data would usually transfer properly from clock domain X to clock domain Y. Occasionally, however, the X and Y domain clocks would have pulses that change so close together in time that the set-up or hold time requirements for output flip flop 146 would not be met. This would cause a metastable state and the signal output by output flip flop 146 may or may not have the correct value. Settling flip flop 144 introduces a one Y clock period delay that permits any metastability to be resolved. If one Y clock period is insufficient to permit the metastability to resolve to a desired level of confidence, then additional settling flip flops are inserted in the path between the two domains.
YX synchronizer 150 is symmetric with respect to XY synchronizer 140. Thus, in YX synchronizer 150, input flip flop 152 is clocked by the Y clock and receives signal S(YX) from clock domain Y 120. Settling and output flip flops 154 and 156, respectively, are both clocked by the X clock. Output flip flop 156 provides synchronized signal S'(YX) as output to clock domain X 110.
It will be appreciated that the prior art synchronizer illustrated in FIG. 1 suffers from significant shortcomings. In particular, settling flip flops 144 and 154 each introduce a one clock period delay. Speed and performance have taken on increased significance in recent digital designs, however. Modern computer systems demand the use of high frequency clocking, while also requiring minimal system failures, and little, if any, synchronizer delay. The trend toward high speed and high performance can be expected to continue, as faster and faster computer systems are designed and implemented. Accordingly, the insertion of a settling delay period whenever a signal crosses a clock domain border is increasingly less desirable.